Over ten years ago I put aside my copy of the HP Journal, December 1996 edition for later reading. I would like to relate some thoughts I have recently had on an article in it.
As pin counts of integrated circuits have continued to rise, the difficulties in arranging wire bonds -- which connect the "pads" on the chip (die) to the landing zones on the "pins" that connect through the "device" (plastic or ceramic) to the outside world -- have likewise continued to rise. As the connections get closer, simply putting pads around the edge of the die makes them too close, and too small, to accurately bond with a flying piece of semi-molten gold wire.
The article shows micrographs of HP's technique for radially staggered bonding. This does increase the available size and separation of the pads but it really only defers the problem. Another problem with device yield is that the "street" which is traditionally cut by a saw requires a significant amount of area.
For a better overall solution, consider the bee's honeycomb.
A honeycomb is a matrix of hexagons. Not only is every cell nearly the same, but the amount of material used to construct the honeycomb is minimized.
If a silicon wafer were cut into hexagons, perhaps by a laser, that would reduce the amount of area lost. Further, because a hexagon more closely approximates a circle -- which is the end convergence of the radially staggered bonding process. (The clue is, "radial" -- think ... circle!)
This whole process could significantly increase both yield and pin count.